//this is a module that can generate T
//Last modified by yangjao at 2021/5/12

module T_generator(
    input wire clk,
    input wire rst_n,
    input wire bigger32,
    input wire bigger15,
    input wire bigger64,
    input wire hash_reg_en,
    input wire restart,
    output wire[31:0] T
);

parameter T1 = 32'h79cc4519;
parameter T2 = 32'h7a879d8a;

reg[31:0] T_out;
reg bigger15_0, bigger15_1;
reg bigger32_0, bigger32_1;
reg bigger64_0, bigger64_1;

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        bigger15_0 <= 0;
        bigger15_1 <= 0;
    end else begin
        bigger15_0 <= bigger15;
        bigger15_1 <= bigger15_0;
    end
end

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        bigger32_0 <= 0;
        bigger32_1 <= 0;
    end else begin
        bigger32_0 <= bigger32;
        bigger32_1 <= bigger32_0;
    end
end

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        bigger64_0 <= 0;
        bigger64_1 <= 0;
    end else begin
        bigger64_0 <= bigger64;
        bigger64_1 <= bigger64_0;
    end
end

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        T_out <= T1;
    end else if(restart)begin
        T_out <= T1;
    end else if(!bigger15_1 && bigger15_0)begin
        T_out <= (T2 << 16)|(T2 >> 16);     //此时需要从T1切换到T2
    end else if((!bigger32_1 && bigger32_0) || (!bigger64_1 && bigger64_0))begin
        T_out <= T2;    //此时j mod 32为0，输出T2
    end else if(hash_reg_en) begin
        T_out <= (T_out << 1)|(T_out >> 31); //不断左移1位
    end
end


assign T = T_out;

endmodule